// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  blk_sch_cfg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  Yau Shek Fan
// Version       :  1.0
// Date          :  2017/7/10
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Yau Shek Fan 2018/03/19 11:46:49 Create file
// ******************************************************************************

#ifndef __BLK_SCH_CFG_REG_OFFSET_H__
#define __BLK_SCH_CFG_REG_OFFSET_H__

/* BLK_SCH_CFG Base address of Module's Register */
#define SOC_BLK_SCH_CFG_BASE                       (0x0)

/******************************************************************************/
/*                      SOC BLK_SCH_CFG Registers' Definitions                            */
/******************************************************************************/

#define SOC_BLK_SCH_CFG_BSC_INIT_REG                     (SOC_BLK_SCH_CFG_BASE + 0x0)   
#define SOC_BLK_SCH_CFG_BSC_MAIN_CFG_REG                 (SOC_BLK_SCH_CFG_BASE + 0x4)   /* Block scheduler config */
#define SOC_BLK_SCH_CFG_BSC_TSC_CFG_REG                  (SOC_BLK_SCH_CFG_BASE + 0x8)   /* Task slot controller config */
#define SOC_BLK_SCH_CFG_BSC_MSBO_CFG_REG                 (SOC_BLK_SCH_CFG_BASE + 0xC)   
#define SOC_BLK_SCH_CFG_BSC_BO_PRI_REG                   (SOC_BLK_SCH_CFG_BASE + 0x10)  
#define SOC_BLK_SCH_CFG_BSC_BO_CNT_REG                   (SOC_BLK_SCH_CFG_BASE + 0x14)  
#define SOC_BLK_SCH_CFG_BSC_BO_CODE_REG                  (SOC_BLK_SCH_CFG_BASE + 0x18)  
#define SOC_BLK_SCH_CFG_BSC_CMD_TO_CNT_LO_REG            (SOC_BLK_SCH_CFG_BASE + 0x1C)  
#define SOC_BLK_SCH_CFG_BSC_CMD_TO_CNT_HI_REG            (SOC_BLK_SCH_CFG_BASE + 0x20)  
#define SOC_BLK_SCH_CFG_BSC_DEBUG_PAUSE_REG              (SOC_BLK_SCH_CFG_BASE + 0x24)  
#define SOC_BLK_SCH_CFG_BSC_RESET_OVERHEAD_REG           (SOC_BLK_SCH_CFG_BASE + 0x28)  
#define SOC_BLK_SCH_CFG_BSC_SECURE_CODE_REG              (SOC_BLK_SCH_CFG_BASE + 0x2C)  
#define SOC_BLK_SCH_CFG_BSC_MAIN_SCH_LITE_CFG_REG        (SOC_BLK_SCH_CFG_BASE + 0x30)  
#define SOC_BLK_SCH_CFG_BSC_ERROR_CLR_REG                (SOC_BLK_SCH_CFG_BASE + 0x34)  
#define SOC_BLK_SCH_CFG_BSC_INT_REG                      (SOC_BLK_SCH_CFG_BASE + 0x40)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DONE_INT_REG            (SOC_BLK_SCH_CFG_BASE + 0x44)  /* Done interrupt form taskslot */
#define SOC_BLK_SCH_CFG_BSC_TASK_DEBUG_INT_REG           (SOC_BLK_SCH_CFG_BASE + 0x48)  /* Debug interrupt from taskslot */
#define SOC_BLK_SCH_CFG_BSC_TASK_EXCEPTION_INT_REG       (SOC_BLK_SCH_CFG_BASE + 0x4C)  /* Exception interrupt from taskslot */
#define SOC_BLK_SCH_CFG_BSC_INT_MSK_REG                  (SOC_BLK_SCH_CFG_BASE + 0x50)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DONE_INT_MSK_REG        (SOC_BLK_SCH_CFG_BASE + 0x54)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DEBUG_INT_MSK_REG       (SOC_BLK_SCH_CFG_BASE + 0x58)  
#define SOC_BLK_SCH_CFG_BSC_TASK_EXCEPTION_INT_MSK_REG   (SOC_BLK_SCH_CFG_BASE + 0x5C)  
#define SOC_BLK_SCH_CFG_BSC_INT_SET_REG                  (SOC_BLK_SCH_CFG_BASE + 0x60)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DONE_INT_SET_REG        (SOC_BLK_SCH_CFG_BASE + 0x64)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DEBUG_INT_SET_REG       (SOC_BLK_SCH_CFG_BASE + 0x68)  
#define SOC_BLK_SCH_CFG_BSC_TASK_EXCEPTION_INT_SET_REG   (SOC_BLK_SCH_CFG_BASE + 0x6C)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DONE_INT_REG          (SOC_BLK_SCH_CFG_BASE + 0x70)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DEBUG_INT_REG         (SOC_BLK_SCH_CFG_BASE + 0x74)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_EXCEPTION_INT_REG     (SOC_BLK_SCH_CFG_BASE + 0x78)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DONE_INT_MSK_REG      (SOC_BLK_SCH_CFG_BASE + 0x7C)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DEBUG_INT_MSK_REG     (SOC_BLK_SCH_CFG_BASE + 0x80)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_EXCEPTION_INT_MSK_REG (SOC_BLK_SCH_CFG_BASE + 0x84)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DONE_INT_SET_REG      (SOC_BLK_SCH_CFG_BASE + 0x88)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_DEBUG_INT_SET_REG     (SOC_BLK_SCH_CFG_BASE + 0x8C)  
#define SOC_BLK_SCH_CFG_BSC_AICORE_EXCEPTION_INT_SET_REG (SOC_BLK_SCH_CFG_BASE + 0x90)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DFX_INT_REG             (SOC_BLK_SCH_CFG_BASE + 0x94)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DFX_INT_SET_REG         (SOC_BLK_SCH_CFG_BASE + 0x98)  
#define SOC_BLK_SCH_CFG_BSC_TASK_DFX_INT_MSK_REG         (SOC_BLK_SCH_CFG_BASE + 0x9C)  
#define SOC_BLK_SCH_CFG_BSC_TASK_PAUSED_INT_REG          (SOC_BLK_SCH_CFG_BASE + 0xA0)  
#define SOC_BLK_SCH_CFG_BSC_TASK_PAUSED_INT_SET_REG      (SOC_BLK_SCH_CFG_BASE + 0xA4)  
#define SOC_BLK_SCH_CFG_BSC_TASK_PAUSED_INT_MSK_REG      (SOC_BLK_SCH_CFG_BASE + 0xA8)  
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_0_REG            (SOC_BLK_SCH_CFG_BASE + 0x100) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_1_REG            (SOC_BLK_SCH_CFG_BASE + 0x104) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_2_REG            (SOC_BLK_SCH_CFG_BASE + 0x108) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_3_REG            (SOC_BLK_SCH_CFG_BASE + 0x10C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_4_REG            (SOC_BLK_SCH_CFG_BASE + 0x110) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_5_REG            (SOC_BLK_SCH_CFG_BASE + 0x114) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_6_REG            (SOC_BLK_SCH_CFG_BASE + 0x118) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_7_REG            (SOC_BLK_SCH_CFG_BASE + 0x11C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_8_REG            (SOC_BLK_SCH_CFG_BASE + 0x120) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_9_REG            (SOC_BLK_SCH_CFG_BASE + 0x124) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_10_REG           (SOC_BLK_SCH_CFG_BASE + 0x128) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_11_REG           (SOC_BLK_SCH_CFG_BASE + 0x12C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_12_REG           (SOC_BLK_SCH_CFG_BASE + 0x130) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_13_REG           (SOC_BLK_SCH_CFG_BASE + 0x134) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_14_REG           (SOC_BLK_SCH_CFG_BASE + 0x138) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_15_REG           (SOC_BLK_SCH_CFG_BASE + 0x13C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_16_REG           (SOC_BLK_SCH_CFG_BASE + 0x140) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_17_REG           (SOC_BLK_SCH_CFG_BASE + 0x144) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_18_REG           (SOC_BLK_SCH_CFG_BASE + 0x148) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_19_REG           (SOC_BLK_SCH_CFG_BASE + 0x14C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_20_REG           (SOC_BLK_SCH_CFG_BASE + 0x150) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_21_REG           (SOC_BLK_SCH_CFG_BASE + 0x154) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_22_REG           (SOC_BLK_SCH_CFG_BASE + 0x158) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_23_REG           (SOC_BLK_SCH_CFG_BASE + 0x15C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_24_REG           (SOC_BLK_SCH_CFG_BASE + 0x160) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_25_REG           (SOC_BLK_SCH_CFG_BASE + 0x164) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_26_REG           (SOC_BLK_SCH_CFG_BASE + 0x168) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_27_REG           (SOC_BLK_SCH_CFG_BASE + 0x16C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_28_REG           (SOC_BLK_SCH_CFG_BASE + 0x170) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_29_REG           (SOC_BLK_SCH_CFG_BASE + 0x174) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_30_REG           (SOC_BLK_SCH_CFG_BASE + 0x178) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_31_REG           (SOC_BLK_SCH_CFG_BASE + 0x17C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_0_REG         (SOC_BLK_SCH_CFG_BASE + 0x180) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_1_REG         (SOC_BLK_SCH_CFG_BASE + 0x184) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_2_REG         (SOC_BLK_SCH_CFG_BASE + 0x188) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_3_REG         (SOC_BLK_SCH_CFG_BASE + 0x18C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_4_REG         (SOC_BLK_SCH_CFG_BASE + 0x190) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_5_REG         (SOC_BLK_SCH_CFG_BASE + 0x194) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_6_REG         (SOC_BLK_SCH_CFG_BASE + 0x198) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_7_REG         (SOC_BLK_SCH_CFG_BASE + 0x19C) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_8_REG         (SOC_BLK_SCH_CFG_BASE + 0x1A0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_9_REG         (SOC_BLK_SCH_CFG_BASE + 0x1A4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_10_REG        (SOC_BLK_SCH_CFG_BASE + 0x1A8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_11_REG        (SOC_BLK_SCH_CFG_BASE + 0x1AC) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_12_REG        (SOC_BLK_SCH_CFG_BASE + 0x1B0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_13_REG        (SOC_BLK_SCH_CFG_BASE + 0x1B4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_14_REG        (SOC_BLK_SCH_CFG_BASE + 0x1B8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_15_REG        (SOC_BLK_SCH_CFG_BASE + 0x1BC) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_16_REG        (SOC_BLK_SCH_CFG_BASE + 0x1C0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_17_REG        (SOC_BLK_SCH_CFG_BASE + 0x1C4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_18_REG        (SOC_BLK_SCH_CFG_BASE + 0x1C8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_19_REG        (SOC_BLK_SCH_CFG_BASE + 0x1CC) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_20_REG        (SOC_BLK_SCH_CFG_BASE + 0x1D0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_21_REG        (SOC_BLK_SCH_CFG_BASE + 0x1D4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_22_REG        (SOC_BLK_SCH_CFG_BASE + 0x1D8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_23_REG        (SOC_BLK_SCH_CFG_BASE + 0x1DC) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_24_REG        (SOC_BLK_SCH_CFG_BASE + 0x1E0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_25_REG        (SOC_BLK_SCH_CFG_BASE + 0x1E4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_26_REG        (SOC_BLK_SCH_CFG_BASE + 0x1E8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_27_REG        (SOC_BLK_SCH_CFG_BASE + 0x1EC) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_28_REG        (SOC_BLK_SCH_CFG_BASE + 0x1F0) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_29_REG        (SOC_BLK_SCH_CFG_BASE + 0x1F4) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_30_REG        (SOC_BLK_SCH_CFG_BASE + 0x1F8) 
#define SOC_BLK_SCH_CFG_BSC_CORE_CUR_TS_BM_31_REG        (SOC_BLK_SCH_CFG_BASE + 0x1FC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_0_REG        (SOC_BLK_SCH_CFG_BASE + 0x200) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_1_REG        (SOC_BLK_SCH_CFG_BASE + 0x208) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_2_REG        (SOC_BLK_SCH_CFG_BASE + 0x210) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_3_REG        (SOC_BLK_SCH_CFG_BASE + 0x218) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_4_REG        (SOC_BLK_SCH_CFG_BASE + 0x220) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_5_REG        (SOC_BLK_SCH_CFG_BASE + 0x228) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_6_REG        (SOC_BLK_SCH_CFG_BASE + 0x230) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_7_REG        (SOC_BLK_SCH_CFG_BASE + 0x238) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_8_REG        (SOC_BLK_SCH_CFG_BASE + 0x240) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_9_REG        (SOC_BLK_SCH_CFG_BASE + 0x248) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_10_REG       (SOC_BLK_SCH_CFG_BASE + 0x250) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_11_REG       (SOC_BLK_SCH_CFG_BASE + 0x258) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_12_REG       (SOC_BLK_SCH_CFG_BASE + 0x260) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_13_REG       (SOC_BLK_SCH_CFG_BASE + 0x268) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_14_REG       (SOC_BLK_SCH_CFG_BASE + 0x270) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_15_REG       (SOC_BLK_SCH_CFG_BASE + 0x278) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_16_REG       (SOC_BLK_SCH_CFG_BASE + 0x280) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_17_REG       (SOC_BLK_SCH_CFG_BASE + 0x288) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_18_REG       (SOC_BLK_SCH_CFG_BASE + 0x290) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_19_REG       (SOC_BLK_SCH_CFG_BASE + 0x298) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_20_REG       (SOC_BLK_SCH_CFG_BASE + 0x2A0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_21_REG       (SOC_BLK_SCH_CFG_BASE + 0x2A8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_22_REG       (SOC_BLK_SCH_CFG_BASE + 0x2B0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_23_REG       (SOC_BLK_SCH_CFG_BASE + 0x2B8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_24_REG       (SOC_BLK_SCH_CFG_BASE + 0x2C0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_25_REG       (SOC_BLK_SCH_CFG_BASE + 0x2C8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_26_REG       (SOC_BLK_SCH_CFG_BASE + 0x2D0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_27_REG       (SOC_BLK_SCH_CFG_BASE + 0x2D8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_28_REG       (SOC_BLK_SCH_CFG_BASE + 0x2E0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_29_REG       (SOC_BLK_SCH_CFG_BASE + 0x2E8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_30_REG       (SOC_BLK_SCH_CFG_BASE + 0x2F0) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_LO_31_REG       (SOC_BLK_SCH_CFG_BASE + 0x2F8) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_0_REG        (SOC_BLK_SCH_CFG_BASE + 0x204) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_1_REG        (SOC_BLK_SCH_CFG_BASE + 0x20C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_2_REG        (SOC_BLK_SCH_CFG_BASE + 0x214) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_3_REG        (SOC_BLK_SCH_CFG_BASE + 0x21C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_4_REG        (SOC_BLK_SCH_CFG_BASE + 0x224) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_5_REG        (SOC_BLK_SCH_CFG_BASE + 0x22C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_6_REG        (SOC_BLK_SCH_CFG_BASE + 0x234) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_7_REG        (SOC_BLK_SCH_CFG_BASE + 0x23C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_8_REG        (SOC_BLK_SCH_CFG_BASE + 0x244) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_9_REG        (SOC_BLK_SCH_CFG_BASE + 0x24C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_10_REG       (SOC_BLK_SCH_CFG_BASE + 0x254) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_11_REG       (SOC_BLK_SCH_CFG_BASE + 0x25C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_12_REG       (SOC_BLK_SCH_CFG_BASE + 0x264) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_13_REG       (SOC_BLK_SCH_CFG_BASE + 0x26C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_14_REG       (SOC_BLK_SCH_CFG_BASE + 0x274) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_15_REG       (SOC_BLK_SCH_CFG_BASE + 0x27C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_16_REG       (SOC_BLK_SCH_CFG_BASE + 0x284) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_17_REG       (SOC_BLK_SCH_CFG_BASE + 0x28C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_18_REG       (SOC_BLK_SCH_CFG_BASE + 0x294) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_19_REG       (SOC_BLK_SCH_CFG_BASE + 0x29C) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_20_REG       (SOC_BLK_SCH_CFG_BASE + 0x2A4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_21_REG       (SOC_BLK_SCH_CFG_BASE + 0x2AC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_22_REG       (SOC_BLK_SCH_CFG_BASE + 0x2B4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_23_REG       (SOC_BLK_SCH_CFG_BASE + 0x2BC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_24_REG       (SOC_BLK_SCH_CFG_BASE + 0x2C4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_25_REG       (SOC_BLK_SCH_CFG_BASE + 0x2CC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_26_REG       (SOC_BLK_SCH_CFG_BASE + 0x2D4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_27_REG       (SOC_BLK_SCH_CFG_BASE + 0x2DC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_28_REG       (SOC_BLK_SCH_CFG_BASE + 0x2E4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_29_REG       (SOC_BLK_SCH_CFG_BASE + 0x2EC) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_30_REG       (SOC_BLK_SCH_CFG_BASE + 0x2F4) 
#define SOC_BLK_SCH_CFG_BSC_PHY_CORE_ADR_HI_31_REG       (SOC_BLK_SCH_CFG_BASE + 0x2FC) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_0_REG           (SOC_BLK_SCH_CFG_BASE + 0x300) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_1_REG           (SOC_BLK_SCH_CFG_BASE + 0x304) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_2_REG           (SOC_BLK_SCH_CFG_BASE + 0x308) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_3_REG           (SOC_BLK_SCH_CFG_BASE + 0x30C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_4_REG           (SOC_BLK_SCH_CFG_BASE + 0x310) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_5_REG           (SOC_BLK_SCH_CFG_BASE + 0x314) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_6_REG           (SOC_BLK_SCH_CFG_BASE + 0x318) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_7_REG           (SOC_BLK_SCH_CFG_BASE + 0x31C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_8_REG           (SOC_BLK_SCH_CFG_BASE + 0x320) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_9_REG           (SOC_BLK_SCH_CFG_BASE + 0x324) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_10_REG          (SOC_BLK_SCH_CFG_BASE + 0x328) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_11_REG          (SOC_BLK_SCH_CFG_BASE + 0x32C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_12_REG          (SOC_BLK_SCH_CFG_BASE + 0x330) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_13_REG          (SOC_BLK_SCH_CFG_BASE + 0x334) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_14_REG          (SOC_BLK_SCH_CFG_BASE + 0x338) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_15_REG          (SOC_BLK_SCH_CFG_BASE + 0x33C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_16_REG          (SOC_BLK_SCH_CFG_BASE + 0x340) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_17_REG          (SOC_BLK_SCH_CFG_BASE + 0x344) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_18_REG          (SOC_BLK_SCH_CFG_BASE + 0x348) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_19_REG          (SOC_BLK_SCH_CFG_BASE + 0x34C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_20_REG          (SOC_BLK_SCH_CFG_BASE + 0x350) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_21_REG          (SOC_BLK_SCH_CFG_BASE + 0x354) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_22_REG          (SOC_BLK_SCH_CFG_BASE + 0x358) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_23_REG          (SOC_BLK_SCH_CFG_BASE + 0x35C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_24_REG          (SOC_BLK_SCH_CFG_BASE + 0x360) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_25_REG          (SOC_BLK_SCH_CFG_BASE + 0x364) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_26_REG          (SOC_BLK_SCH_CFG_BASE + 0x368) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_27_REG          (SOC_BLK_SCH_CFG_BASE + 0x36C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_28_REG          (SOC_BLK_SCH_CFG_BASE + 0x370) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_29_REG          (SOC_BLK_SCH_CFG_BASE + 0x374) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_30_REG          (SOC_BLK_SCH_CFG_BASE + 0x378) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_31_REG          (SOC_BLK_SCH_CFG_BASE + 0x37C) 
#define SOC_BLK_SCH_CFG_BSC_VIRTUAL_CORE_STATUS_REG      (SOC_BLK_SCH_CFG_BASE + 0x380) 

#endif // __BLK_SCH_CFG_REG_OFFSET_H__
